1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a method for implanting silicon into select areas of a refractory metal to reduce the consumption of silicon-based junctions underlying those select areas during salicide formation.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the impurity regions. Interconnect routing is then placed across the semiconductor topography and connected to the impurity regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is described generally as "metallization". As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased. Conductive materials other than metal are commonly used for metallization. As such, the term metallization is generic in its application.
Integrated circuits often employ active devices known as transistors. A transistor includes a pair of impurity regions, i.e., junctions, spaced apart by a gate conductor which is dielectrically spaced above the substrate within which the junctions reside. The junctions contain a dopant species opposite in type to that of a channel region residing underneath the gate conductor. Formation of an ohmic contact through an interlevel dielectric to a junction involves patterning a protective mask upon areas of the interlevel dielectric exclusive of where the ohmic contact is to be formed. The area of the interlevel dielectric left uncovered by the mask is then etched to form an opening or window directly above the junction to which contact is to be made. The contact window is then filled with a conductive material. Unfortunately, the mask, and hence the contact, may be misaligned with the junction, resulting in increased resistance at the interface between the contact and the junction.
It has therefore become necessary to incorporate self-aligned, low resistivity structures between the contact windows and the junctions to ensure that contact is made to the entire area of the junction. More specifically, low resistivity structures referred to as self-aligned suicides, or salicides are commonly formed upon the junctions of a silicon-based substrate. A salicide process involves depositing a refractory metal across the semiconductor topography, and then reacting the metal only in regions where a high concentration of silicon atoms are present. In this manner, salicides may be formed exclusively upon the junctions and the upper surface of a polycrystalline silicon ("polysilicon") gate conductor interposed between the junctions. Salicide formed upon polysilicon is generally referred to as polycide. Regions between the junctions and the sidewall surfaces of the gate conductor may be pre-disposed with dielectric sidewall spacers generally formed from silicon dioxide ("oxide"). The sidewall spacers serve to prevent the metal deposited across the semiconductor topography from contacting, and hence reacting with, the polysilicon at the sidewall surfaces of the gate conductor. Absent the sidewall spacers, silicide could form upon the sidewall surfaces of the gate conductor, undesirably shorting the gate conductor to the adjacent junctions.
Unfortunately, silicide formation upon the dielectric sidewall spacers is still possible in some situations. In particular, when titanium is used as the refractory metal, annealing the titanium within a conventional furnace at temperatures above about 700.degree. C. may lead to lateral interdiffusion between the titanium atoms and the silicon atoms of the spacers. It is believed that the silicon atoms are provided from broken Si--O bonds. The titanium atoms and the silicon atoms readily react to form TiSi.sub.2 upon the sidewall spacers. The lateral formation of silicide between the gate conductor and the junctions can "bridge"the separation between the structures, causing the gate to be shorted to the junctions. To overcome this problem, a two-step anneal process may be employed to form titanium salicide. The first anneal step forms a first phase TiSi.sub.2 at a relatively low temperature of less than 700.degree. C. to prevent substantial interdiffusion between the titanium and silicon within the adjoining sidewall surfaces. The unreacted titanium is then removed from the non-silicon-based surfaces, e.g., the sidewall spacers, in the interim between the first and second anneal steps. The second anneal step may then be performed at a temperature greater than 800.degree. C. to form a second phase TiSi.sub.2 having a lower resistance than the first phase.
Device dimensions of an integrated circuit are continuously being reduced to afford increased circuit speed and complexity. As the distance between the source junction and the drain junction of a transistor (i.e., the physical channel length) decreases, the junction areas must also be reduced to prevent unwanted source/drain-tosubstrate junction capacitance. Unfortunately, as junctions become more shallow, e.g., less than 1,000 .ANG. in depth, consumption of the silicon within the junctions may lead to problems. In particular, conventional salicide processing typically results in 100 .ANG. to 200 .ANG. of a junction being consumed. Interdiffusion between silicon of the junctions and the refractory metal, particularly titanium, can be so extensive that in some instances the metal can "spike" through relatively shallow junctions. As a result of the metal penetrating below the depth of the junctions into the bulk substrate, the junctions may experience large current leakage or even become electrically shorted. These problems may become paramount as junction depth continues to decrease to below 500 .ANG..
Various techniques have been developed to minimize the occurrence of junction spiking. FIGS. 1-3 depict one of these techniques. FIG. 1 illustrates a silicon-based substrate 20 upon and within which a transistor has been formed. The transistor is bounded by field isolation structures 21 which have been formed using a shallow trench isolation process. A polysilicon gate conductor 24 is spaced above substrate 20 by a gate oxide 22. Oxide sidewall spacers 26 extend laterally from the opposed sidewall surfaces of gate conductor 24. Lightly doped drain ("LDD") areas 28 of substrate 20 are arranged directly beneath sidewall spacers 26. Source and drain regions 30 are positioned within substrate 20 laterally between LDD areas 28 and field isolation structures 21. Source and drain regions 30 and LDD areas 28 form graded junctions within substrate 20 which increase in dopant concentration in a lateral direction away from gate conductor 24. According to the more modern salicidation process, a relatively thin layer (less than 100 .ANG.) of amorphous silicon 32 (i.e., .alpha. Si) is deposited across the semiconductor topography.
As shown in FIG. 2, a refractory metal 34 is then deposited across the layer of amorphous silicon 32. Refractory metal 34 is subjected to a thermal cycle 36 to promote the formation of silicide upon heavily concentrated silicon-based surfaces. Since metal atoms can react with silicon atoms of the adjacent amorphous layer 32 rather than with silicon atoms of substrate 20 the depletion of source and drain regions 30 is reduced. As depicted in FIG. 3a, the unreacted portions of refractory metal 34 may be removed while salicide structures 38 are retained upon source and drain regions 30 and polycide structure 40 is retained upon the upper surface of gate conductor 24. While the amorphous layer of silicon 32 is relatively thin, its presence upon sidewall spacers 26 can lead to the formation of silicide upon the spacers. FIG. 3b depicts a detailed view along section 3b of FIG. 3a in which such a silicide layer 44 has been formed upon sidewall spacer 26. Silicide layer 44 could undesirably form a conductive path between gate conductor 24 and source and drain regions 30.
FIGS. 4-5 illustrate another method which has been employed to counter the consumption of junctions during the salicidation process. FIG. 4 depicts a silicon-based substrate 50 in which trench isolation structures 51 have been formed a spaced distance apart. A transistor has been fabricated upon and within an active area of substrate 50 between trench isolation structures 51. The transistor includes a gate conductor 54, a gate oxide 52, LDD areas 58, and source and drain regions 60. Oxide sidewall spacers are interposed between gate conductor 54 and source and drain regions 60. Salicide structures 62 and polycide structure 66 are formed according to the two-step anneal process described above. As shown in FIG. 5, dopant species similar in type to those residing within source and drain regions 60 are implanted at a relatively high energy into regions of the substrate below source and drain regions 60. In this manner, unactivated junction areas 68 are formed beneath activated source and drain regions 60. Even though metal may have penetrated all the way through source and drain regions 60 during salicide formation, the presence of unactivated junction areas 68 prevents the metal from contacting the oppositely doped bulk substrate 50.
One drawback of forming unactivated junction areas is that additional masking steps are required to implant p-type species exclusively into active areas occupied by PMOS transistors and n-type species exclusively into active areas occupied by NMOS transistors. That is, the NMOS transistors must be masked during the implant of p-type species, and vice versa. The additional masking steps would add to the overall time required to produce each integrated circuit device, decreasing the throughput of the integrated circuit manufacturer. In addition to this drawback, relatively large dopant species, e.g., arsenic, implanted through the silicide may strike metal atoms (e.g., Co or Ti) at a force sufficient to dislodge the atoms. Consequently, the metal atoms may be repelled into the channel region of substrate 50 underneath gate conductor 54. Unfortunately, the presence of the metal atoms within the channel could increase the subthreshold current of the transistor in its off-state.
It would therefore be desirable to develop a process for forming a salicide without being concerned that excessive consumption of the junctions might lead to junction spiking. Further, salicide formation upon the sidewall spacers laterally adjacent the gate conductor must be eliminated to ensure that silicide bridging between the gate conductor and the junctions does not occur. Accordingly, the sidewall spacers must be maintained absent of silicon atoms other than those bonded within the spacers. Also, formation of contacts to relatively shallow junctions must not be performed at the expense of increasing the leakage of current between the junctions. As such, implanting additional dopant species through the salicide should be avoided to prevent metal atoms of the salicide from being knocked into the channel.